TRIAL ONE ENTRY PAGE
(Combinational Logic)


TRIAL ONE: Revision of digital logic gates, use of a simple digital trainer for hardware experiments and a practical task to apply this knowledge.
SECTION INDEX
  1. Revision of Combinational Logic and Introduction to the Digital Logic Trainer.
  2. Introduction to the Practical Task and the creation of segment select circuits.
  3. Details of the 7 Segment Display and the use of segment selection circuits to drive it.
  4. The use of a CMOS 4511 BCD to 7 Segment Latch Decoder Driver as part of Prcatical Task.
1. Revision of Combinational Logic and Introduction the Digital Logic Trainer.


The revision material was worked through with the student before moving on to the digital trainer. A CMOS 4081 Quad two input AND gate was used to introduce manufacturer data sheets as a source of gate connection information. The revision material used was part of this course which can be accessed HERE.
The digital trainer has two slide switches generating logic 1 or logic 0 which are used to provide an input to curcuits being tested. These two switches can be used as a two digit binary number gives four possible combinations. The trainer also uses a special connecting method for prototyping circuits without solder. The details of this type of board are given HERE.
The CMOS 4081 Quad two input AND Gate was put into the prototype board as shown in the photograph below.


The rows of pins are plugged in either side of the central division between the rows of holes. In this way, each pin is connected to an individual row of holes. The Data sheet for the 4081 is then examined and the pin connection numbers for the two inputs and the output of one of the four AND gates noted. The other pin numbers required are VDD which is connected to +V on the prototype board, and VSS which is connected to 0V on the prototype board. A lead from one switch is connected to one of the selected AND gate input pin. The other switch is connected to the other AND gate input pin. The build section is started selecting an AND gate to use from the four on the 4081 and connected as above. Testing will be confirmation that operation of the chip is as described by the TRUTH TABLE for an AND gate.

2. Introduction to the Practical Task and the creation of the segment selection corcuits.


The task was to decode the switch values and display the decimal equivalent value on a seven segment display. The first stage of this task was to calculate the boolean expression for each of the seven segments in terms of the two logic switch values. The circuit using AND, OR and NOT for each of the segments was then designed. [Boolean Algebra was used to simplify the expression before designing the circuit]. The diagrams below shows the arrangement of the seven segments on the seven segment display.
The next stage in designing the segment selection circuits is to make a table of all the information we have been given. The four diagrams of the seven segment display for "0" to "3" show which segments are ON and which are OFF. This is added the table together with the binary values of switches A and B for "0" to "3".
DISPLAY B A segment a segment b segment c segment d segment e segment f segment g
0 0 ON ON ON ON ON ON OFF
0 1 OFF ON ON OFF OFF OFF OFF
1 0 ON ON OFF ON ON OFF ON
1 1 ON ON ON ON OFF OFF ON


DESIGN EXAMPLE: Segment "a"

If we examine the column for segment "a" in the table we see it is ON for three binary values and OFF for one. The design can be simplified by making a cicuit that generates a LOGIC 0 when the segment should be OFF. One design is to detect the binary value 01, NOT B and A, and inverting it. This gives not( NOT B andA). Using De Morgans theorem we get NOT NOT B or NOT A, which simpifies to B or NOT A. The simplest way to prove if this is correct is use a TRUTH TABLE.
B A NOT A B or NOT A
0 0 1 1
0 1 0 0
1 0 1 1
1 1 0 1

The next step is to compare the output pattern in the TRUTH TABLE to the pattern for segment A in the DESIGN INFORMATION TABLE. They are identical, proving that a curcuit implementing the logic expression B or NOT A will drive Segment "a" correctly. Some design work can be done by examining the DESIGN INFORMATION TABLE closely. This process is known in Maths as INSPECTION.
  • Segment "b" is ON for all four combinations of A and B. The segment selection signal is therefore simply a wire from +V to Segment "b"!

  • Segment "c" is ON for all combinations except when B is ON and A is OFF. The design process is similar to that of Segment "a" where the OFF condition is detected and INVERTED to provide the segment selection signal.

  • Segment "d" is ON for all the same combinations of A and B as Segment "a". The segment selection curcuit is therefore the same as Segment "a".

  • Segment "e" is ON for all combinations when A is OFF. The segment selection signal is therefore not A. It can be seen from the DESIGN INFORMATION TABLE that the state of B does not affect the segment output. The state of B is often called a "do not care" state as it has no effect on the output.

  • Segment "f" is ON only when A and B are both OFF. The segment selection signal is not (NOT B and NOT A), which can be shown to be not (A or B).

  • Segment "g" is ON for all combinations when B is ON. The segment selection signal is therefore simply B! A is a "do not care" state in this case.
{ NOTE: the simplification using "do not care" states is VALID in this case as the inputs are from two binary switches so only four states are possible. For systems which use more than two bits, binary digits, then all the bits should be decoded to ensure that values "0" to "3" are correctly detected.]

A driver circuit is required to drive each segment as logic output from a gate is not able to supply enough current to drive an LED segment. The driver circuit and how it is used can be found in section three.

3. Details of the 7 Segment Display and the use of segment selection circuits to drive it.
The image below shows the seven segment driver board designed for Trial1. The small circuit board on the end of the ribbon cables has pins spaced according the Dual In Line, or DIL, standard. This is the same as the devices and the prototype boards on the trainer. The connector formed by the small circuit board enables the driver board to be plugged in as another "device" in the circuit.







Driver circuit connections

Seven segment display connections
USE OF THE DRIVER CIRCUIT

The seven inputs, "a" to "g", are connected to the corresponding outputs on the segment select circuits built on the digital trainer. The seven outputs, "a out" to "g out" are connected to the corresponding inputs, "a" to "g", on the seven segment display. The 0 Volt [pin 8] on the 16 pin driver circuit connector must be connected to 0 Volt on the Digital trainer. This links the 0 volt of all the seven driver circuits to the same 0 volt as the digital logic curcuits on the trainer. One of the connection marked common on the seven segment display must be connected to +V on the trainer. It is called common as it is connected internally to the anode of each of the LEDs in the display. More details as to why this is important are to found in section Four.
MONITOR OUTPUTS
The connection strip on one edge of the driver circuit provides access to "a" to "g" segment signals and 0 Volts coming into the driver circuit. The +V [pin 16] of the driver circuit connector needs a connection to +V on the digital trainer to make it available on the MONITOR OUTPUT strip. The MONITOR OUTPUT strip may be useful for the final part of this trial using the 4511 CMOS BCD-to-7-Segment Latch Decoder Driver chip.


4. The use of a CMOS 4511 BCD to 7 Segment Latch Decoder Driver as part of Practical Task.

This final section of Trial1 uses a CMOS 4511 BCD to 7 segment decoder chip to replace the segment selection circuits and the display driver used up to this point in the trial. The internal circuit diagram of the chip in the data sheet shows the decoding circuits for the 7 segments for the digits "0" to "9". Four bits are needed to encode these digits as binary values 0000 to 1001. This use of 4 bit binary to encode each decimal number is called BINARY CODED DECIMAL, abreviated to BCD.



4511 CMOS BCD-to-7-Segment Latch Decoder Drivers
[NOTE: There are two different types of 7 segment display, one has all the Anodes of the 7 leds connected together called COMMON ANODE, or CA. The other type has all the cathodes of the 7 leds connected together called COMMON CATHODE, or CC. The display we have been working with is a CA type where all the ANODES are connected to +V and the segments are lit by connecting each individual led to 0 V via a resistor. This task in our system was carried out by the seven segment driver board. We will still need to use this board between the outputs "a" to "g" on the 4511 chip and the 7 segment display. This is because the 4511 is designed for CC type displays and our driver board converts the output of the chip to match the CA type display.]


CONNECTION TO THE 4511 CHIP

PIN NO. PIN NAME PIN USE
1 B One of the four BCD inputs
2 C One of the four BCD inputs
3 NOT LT Lamp Test: Forces all Segments to be lit when input LOW(indicated by NOT in name)
4 NOT BL Blanking: Forces all segments to be Blank, i.e. OFF, when input LOW (indicated by NOT in name)
5 LE / NOT STROBE Latch Enable for BCD inputs to control display outputs when HIGH / Display outputs held at BCD values that existed when signal went LOW
6 D One of the four BCD inputs
7 A One of the four BCD inputs
8 VSS 0 Volt Power Supply connection
9 e out Output to Segment "e" [via seven segment driver board see NOTE above]
10 d out Output to Segment "d" [via seven segment driver board see NOTE above]
11 c out Output to Segment "c" [via seven segment driver board see NOTE above]
12 b out Output to Segment "b" [via seven segment driver board see NOTE above]
13 a out Output to Segment "a" [via seven segment driver board see NOTE above]
14 g out Output to Segment "g" [via seven segment driver board see NOTE above]
15 f out Output to Segment "f" [via seven segment driver board see NOTE above]
16 VDD +V Power Supply Connection (3 - 18 V DC)

The build section requires the 4511 chip to be wired as in the TABLE above. The two switches on the Digital trainer are used as A and B on the BCD inputs. C and D should be connected to 0 Volts to restrict the input to the range "0" to "3".
Testing will with the checking of segment values on the 4511 for "0" to "3". Finally, the seven segment driver board is connected, via the terminal strip, and the 7 segment display used to check correct operation for "0" to "3" on the switches. The 7 segment display is connected to the seven segment driver board as in section 3 above.